376 Appendix C instruction code in the program being executed in the processor. The block arrows used in the diagram indicate the parallel data paths (8-bit in PIC16) which carry the operands to the ALU, and the result away to the next stage. A set of data registers that store the operands is usually associated with the ALU. In the PIC16, the working register (W) always receives the result, and provides one of the operands. In other processors, multiple data registers can provide the operands and store the result. C.8. Processor Control The instruction decoder is a logic circuit in the central processing unit (CPU), which receives the instruction codes from the program to control the sequence of operations. The decoder output lines, which are connected to the registers, ALU, gates and other control logic, are set up for a particular instruction to be carried out (e.g. add two data bytes). The processor control block (Figure C.8) also includes timing control and other logic to manage the processor operations. The clock signal drives the sequence of events, so that after a certain number of clock cycles, the results of the instruction are generated and stored in a suitable register or back in memory. C.9. CPU System Operation Although we are mainly concerned with microcontroller architecture, it is worth looking briefly at memory and I/O access in a conventional system, because it explains the process that occurs within the microcontroller chip, and is important for an overview of microprocessor systems. It is a logical extension of address decoding within each memory chip. The typical microprocessor system consists of memory and I/O devices connected to the CPU by a shared data bus. Only one peripheral chip can use the data bus at any one time, so a system of chip selection is needed whereby the processor can communicate with a particular device. Figure C.9(a) shows the system connections that allow the CPU to read and write Instruction Code Instruction Decoder CPU Sequence Control Control lines to processor registers, ALU, etc. Clock Figure C.8 CPU control logic