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2.1. Three-Dimensional Integration > 2.1.1. System-in-Package - Pg. 18

18 CHAPTER 2 Manufacturing of 3-D Packaged Systems V out V DD n + n + Gate p + p + n FIGURE 2-1 Three-dimensional stacked inverter [34]. A cross section of this inverter is illustrated in Figure 2-1. Several other approaches to three-dimensional integration, however, have been developed, both at the package and circuit level. Bare or packaged die are vertically integrated, permitting a broad variety of interconnection strategies. Each of these vertical interconnection techniques has differ- ent advantages and disadvantages. Other more esoteric technologies for 3-D circuits have also been proposed. To avoid confusion, therefore, a crucial differentiation among the various 3-D integration approaches is maintained in this chapter. Two primary categories of 3-D systems are discerned, namely, system-in-package (SiP) and three-dimensional integrated circuits (3-D ICs). The criterion to distinguish between SiP and 3-D IC is the interconnection technology that provides communi- cation for circuits located on different planes of a 3-D system. In SiP, through silicon vias (TSVs) with high aspect ratios are typically utilized. Due to the size of these vias, a high vertical interconnect density cannot be achieved. Hence, these interconnects provide coarse-grain connec- tivity among circuit blocks located on different planes. Alternatively, in 3-D ICs, fine-grain interconnection among devices on different planes is achieved by narrow and short TSVs. 2.1.1 System-in-Package Henceforth in this book a system-in-package is described as an assem- blage of either bare or packaged die along the third dimension, where the interconnections through the z-axis are primarily implemented through the following means: n n n n Wire bonding Vertical interconnects along the periphery of the die/package Long and wide, low-density vertical interconnects (in an array arranged across the die/package) Metallization between the faces of a 3-D stack Die or package bonding can be implemented by utilizing a diverse collection of materials, such as epoxy and other polymers. Some examples of SiP structures are illustrated in Figure 2-2. Each example of these manufacturing techniques is discussed in Section 2.3. 2.1.2 Three-Dimensional Integrated Circuits Three-dimensional IC manufacturing can be conceptualized either as a sequential or a parallel process. In the case of a sequential process, the devices and metal layers of the upper planes of the stack are grown on top of the first plane. Hence, the 3-D system can be treated as a