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2.3.4. Metallizing the Walls of an SiP > 2.3.4. Metallizing the Walls of an SiP - Pg. 31

2.3 Technologies for System-in-Package 31 Prototypes with as many as seven stacked ICs demonstrate a consid- erably higher integration as compared with a wire-bonded SiP. These prototypes are diced from an initial stack consisting of 70 identical ICs. Producing shorter stacks from a taller cube contributes to a reduction in the overall fabrication time. In addition to memory pro- ducts, an image-capturing and processing system fabricated with a similar technique has been introduced [62], [63]. The entire fabrica- tion process consists of several basic steps. Each IC is attached onto laminated films or, if necessary, a PCB along with discrete passive components. The substrate contains metal tracks, such as copper lines plated with gold, and the I/Os of the IC are wire bonded to these tracks. Each mounted IC is tested before bonding. This testing step improves the total yield as bonding the KGD is guaranteed. Testing includes validation of the interconnections connecting the IC to the laminated film or PCB. The test structures are placed in a plastic mold and encapsulated with an epoxy resin. After removal of the mold, a sawing step is applied to expose the metal tracks of each PCB within