46 CHAPTER 3 3-D Integrated Circuit Fabrication Technologies is etched to expose the silicon for the channel region (Figure 3-6f). Boron doping is used to implement the source and drain regions of the PMOS transistor on the top layer (Figure 3-6g). The active area for the devices is defined by removing the LTO and the buried oxide (Figure 3-6h). Before forming the gates for the stacked tran- sistors, the gate oxide is grown by thermal oxidation, as shown in Figure 3-6i. Finally, in situ deposition of doped polysilicon forms the gate electrodes. Note that for the gate below the channel region of the PMOS transistor (see Figure 3-6j), a slow deposition rate is required to fully fill this region. 3.1.2 3-D Fin-FETs 3-D fin-FETs are based on quasiplanar fin-FETs [80] where the devices are stacked on top of each other, thereby sharing the same gate. A schematic of a 3-D fin-FET CMOS inverter is shown in Figure 3-7 [81], [82]. The second device layer can be either grown on top of the first plane or, alternatively, can be bonded from a second wafer. The most attractive feature of this technology is the approximately 50% reduction in gate area and routing resources to connect the devices within the gate. The drive current of the devices is not con- trolled by the width of the devices, W n and W p , but rather from the corresponding fin height notated as H n and H p for a NMOS and PMOS transistor, respectively, as shown in Figure 3-7. The major steps of a 3-D fin-CMOS process are illustrated in Figure 3-8. A second oxide layer behaves as the buried oxide for the second plane. A silicon film is grown on top of the buried oxide layer. A mask for the gate, which can endure ion etching, is formed, and inductively plasma-enhanced (ICP) deep reactive ion etching (DRIE) is applied to n FIGURE 3-7 3-D stacked fin-CMOS device [81]. Channel length, L H n NMOS NMOS Source Source Insulator PMOS Source Source Shared gate NMOS Drain Insulator Insulator PMOS Drain Drain H p Buried oxide