130 CHAPTER 6 Thermal Management Techniques power density blocks is avoided. The integrated thermal via planning and floorplanning approach is compared with a nonintegrated approach, where the floorplan (initially omitting the thermal objec- tives) is generated first followed by thermal via planning as a postpro- cessing step. The integrated technique requires 16% fewer thermal vias for the same temperature constraint, with a 21% increase in computational time and an almost 3% reduction in the total area. 6.3.3 Thermal Wire Insertion In addition to the benefits that the added thermal vias produce, ther- mal wires can also be utilized to enhance the heat transfer process. These thermal wires correspond to horizontal wires that connect regions with different thermal via densities through thermal inter- plane vias. These thermal wires are treated as routing channels wher- ever there are available tracks. Both thermal interplane vias and wires can be handled during routing [220]. Given a placement of cells within a 3-D IC, the technology parameters, and a temperature constraint, sensitivity analysis and linear programming methods are utilized to route a circuit. For routing purposes, a 3-D grid is imposed on a 3-D circuit as shown in Figure 6-16 for a two-plane 3-D circuit. In addition, the thermal model of a circuit is based on a resistive network, as discussed in subsection 6.1.2. Note that the interconnect power component is not considered in this thermal model [220]. n FIGURE 6-16 Routing grid for a two-plane 3-D IC. Each horizontal edge of the grid is associated with a horizontal wire capacity. Each vertical edge is associated with an interplane via capacity. Cell boundary Thermal wires v i Cell i v i v j v j Cell j Placing thermal vias and wires to decrease the circuit temperature adversely affects the available routing resources while increasing the routing congestion. Each vertical edge of the routing grid is, therefore, associated with a specific capacity of interplane vias. A similar con- straint applies for the horizontal edges, which represent horizontal routing channels. The width of the routing channel can be considered equal to the edge width of the tiles. As shown in Figure 6-17, the thermal wire and vias affect the routing capacity of each tile. The 3-D global routing flow is depicted in Figure 6-18 where thermal vias and wires are inserted to achieve a target temperature under con- gestion and capacity constraints. A 3-D minimum Steiner tree is initi- ally generated, followed by an interplane via assignment. A 2-D maze router produces a thermally driven route within each plane of the circuit. In the following steps [220], an iterative procedure is applied to insert the thermal vias and wires and complete the physical rout- ing. A thermal model and sensitivity analysis are used to perform a linear programming based thermal via and wire insertion in the first Interplane vias n FIGURE 6-17 Impact of a thermal wire on the routing capacity of each grid cell. v i and v j denote the capacity of the interplane vias for cell i and j, respectively. The horizontal cell capacity is equal to the width of the boundary of the cells [220].