198 CHAPTER 9 3-D Circuit Architectures In this chapter, various possible topologies for 3-D NoC are pre- sented. In addition, analytic models for the zero-load latency and power consumption with delay constraints of these networks that capture the effects of the topology on the performance of 3-D NoC are described. Optimum topologies are shown to exist that minimize the zero-load latency and power consumption of a network. These optimum topologies depend on a number of parameters characteriz- ing both the router and the communication channel, such as the number of ports of the network, the length of the communication channel, and the impedance characteristics of the interconnect. Vari- ous trade-offs among these parameters that determine the minimum latency and power consumption topology of a network are investi- gated for different network sizes. A cycle-accurate simulator for 3-D topologies is also discussed. This tool is used to investigate the behav- ior of several 3-D topologies under broad traffic scenarios. Several interesting topologies, which are the topic of this chapter, emerge by incorporating the third dimension in NoC. In the follow- ing section, various topological choices for 3-D NoC are reviewed. In Section 9.3.2, an analytic model of the zero-load latency of tradi- tional interconnection networks is adapted for each of the proposed 3-D NoC topologies, while the power consumption model of these network topologies is described in Section 9.3.3. In Section 9.3.4, the 3-D NoC topologies are compared in terms of the zero-load net- work latency and power consumption with delay constraints, and guidelines for the optimum design of speed-driven or power-driven NoC structures are provided. An advanced NoC simulator, which is used to evaluate the performance of a broad variety of 3-D network topologies, is presented in Section 9.3.5. 9.3.1 3-D NoC Topologies Various topologies for 3-D networks are presented, and related termi- nology is introduced in this section. Mesh structures have been a popu- lar network topology for conventional 2-D NoC [269], [270]. A fundamental element of a mesh network is illustrated in Figure 9-10a, where each processing element (PE) is connected to the network through a router. A PE can be integrated either on a single physical plane (2-D IC) or on several physical planes (3-D IC). Each router in a 2-D NoC is connected to a neighboring router in one of four directions. Consequently, each router has five ports. Alternatively, in a 3-D NoC, the router typically connects to two additional neighboring routers located on the adjacent physical planes. The architecture of the router