204 CHAPTER 9 3-D Circuit Architectures Also, since a repeater insertion methodology for minimum latency is applied, any further reduction in latency is due to the network topology. The length of the vertical communication channel for the 3-D NoC shown in Figure 9-10 is 8 > L v ; < l v ¼ n p L v ; > : 0; for 2DIC À 3D NoC; for 3DIC À 3D NoC; for 2DIC À 2D NoC and 3DIC À 2D NoC; ð9-17aÞ ð9-17bÞ ð9-17cÞ ( p ffiffiffiffiffiffiffiffiffi for 2DIC À 2D NoC and 2DIC À 3D NoC; A PE ; À Á p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1:12 A PE = n p ; for 3DIC À 2D NoC and 3DIC À 3D NoC n p > 1 ; where L v is the length of a silicon-through (interplane) via connecting two routers on adjacent physical planes. n p is the number of physical planes used to integrate each PE. The length of the horizontal com- munication channel is assumed to be ð9-18aÞ ð9-18bÞ where A PE is the area of the processing element. The area of all of the