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206 CHAPTER 9 3-D Circuit Architectures The total power consumption with delay constraint T 0 for a single line of a crossbar switch P stotal , horizontal buss P htotal , and vertical buss P vtotal is, respectively, P stotal ð T 0 À t a Þ ¼ P di þ P si þ P li; P htotal ð T 0 Þ ¼ P di þ P si þ P li; P vtotal ð T 0 Þ ¼ P di þ P si þ P li : (9-22) (9-23) (9-24) The power consumption of the arbitration logic is not included in (9-22), since most of the power is consumed by the crossbar switch and the buss interconnect, as discussed in [284]. Note that for a crossbar switch, the additional delay t a of the arbitration logic poses a stricter delay constraint on the power consumption of the switch as shown in (9-22). The mini- mum power consumption with delay constraints is determined by the methodology described in [276], for which the optimum size h *powi and number k *powi of the repeaters for a single interconnect line is determined. Consequently, the minimum power consumption per bit between a source destination node pair in a NoC with a delay constraint is P bit ¼ hopsP stotal þ hops 2ÀD P htotal þ hops 3ÀD P vtotal: (9-25) The effect of resistive shielding is also considered in determining the effective interconnect capacitance. Furthermore, since the repeater insertion methodology in [276] minimizes the power consumed by the repeater system, any additional decrease in power consumption is due only to the network topology. In the following section, those 3-D NoC topologies that exhibit the maximum performance and minimum power consumption with delay constraints are presented. Trade-offs in determining these topologies are discussed, and the impact of the network parameters on the resulting optimum topolo- gies is demonstrated for various network sizes. 9.3.4 Performance and Power Analysis for 3-D NoC Several network parameters characterizing the topology of a network can significantly affect the speed and power of a system. The evalua- tion of these network parameters is discussed in Section 9.3.4.1. The improvement in network performance achieved by the 3-D NoC topologies is explored in Section 9.3.4.2. The distribution of nodes that produces the maximum performance is also discussed. The power consumption with delay constraints of a 3-D NoC and the topologies that yield the minimum power consumption of a 3-D NoC are presented in Section 9.3.4.3.