9.3 Three-Dimensional Networks-on-Chip 221 former approach typically benefits small networks, while the latter approach yields lower power consumption for large networks. For medium-sized networks and depending on the network and intercon- nect parameters, nonextreme values for the n 3 and n p parameters (e.g., 1 < n 3 < n max and 1 < n p < n max ) are required to produce the minimum power consumption topology. Note that this work emphasizes the latency and power consumption of a network, neglecting the performance requirements of the individual PEs. If the performance of the individual PEs is important, only one 3-D topology may be available; however, even with this constraint, a sig- nificant savings in latency and power can be achieved since in almost every case the network latency and power consumption can be decreased as compared to a 2-D IC ­ 2-D NoC topology. Furthermore, as previously mentioned, if the available topology is the 2-D IC ­ 3-D NoC, setting n 3 equal to n max is not necessarily the optimum choice. The zero-load network latency and power consumption expressions