Three-dimensional Integrated Circuit Design > Appendix D: Proof of Condition for Via Placement of Multiterminal Nets

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Three-dimensional Integrated Circuit Design

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Table of Contents

Front Cover

Three-Dimensional Integrated Circuit Design

Chapter 1: Introduction

Chapter 2: Manufacturing of 3-D Packaged Systems

Chapter 3: 3-D Integrated Circuit Fabrication Technologies

Chapter 4: Interconnect Prediction Models

Chapter 5: Physical Design Techniques for 3-D ICs

Chapter 6: Thermal Management Techniques

Chapter 7: Timing Optimization for Two-Terminal Interconnects

Chapter 8: Timing Optimization for Multiterminal Interconnects

Chapter 9: 3-D Circuit Architectures

Chapter 10: Case Study: Clock Distribution Networks for 3-D ICs

Chapter 11: Conclusions

Appendix A: Enumeration of Gate Pairs in a 3-D IC

Appendix B: Formal Proof of Optimum Single Via Placement

Appendix C: Proof of the Two-terminal Via Placement Heuristic

Appendix D: Proof of Condition for Via Placement of Multiterminal Nets

References

Index

Appendix Proof of Condition for Via Placement of Multiterminal Nets In this appendix, a proof for necessary condition 1 is provided. Condition 1: If r j > r j þ1, only a type-1 move for v j can reduce the delay of a tree. Proof: Consider Fig D-1 where the interplane via v j (the solid square) D

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Appendix D: Proof of Condition for Via Placement of Multiterminal Nets - Pg. 287