248 CHAPTER 10 Case Study: Clock Distribution Networks for 3-D ICs at MIT Lincoln Laboratories (MITLL). This fabrication process is dis- cussed in the following section. The logic circuitry comprising the common load of the 3-D clock distribution networks is described in Section 10.2. The various clock distribution networks that have been employed in this case study are described in Section 10.3. Experimen- tal results and a comparison of the different clock distribution net- works are presented in Section 10.4. A short summary is provided in the last section of the chapter. 10.1 MIT LINCOLN LABORATORIES 3-D IC FABRICATION TECHNOLOGY The MIT Lincoln Laboratories recently developed a manufacturing pro- cess for fully depleted silicon-on-insulator (FDSOI) 3-D circuits with short interplane vias (also called 3-D vias here for simplicity). The most attractive feature of this process is the high density of the 3-D vias as compared to other 3-D technologies currently under development,