254 CHAPTER 10 Case Study: Clock Distribution Networks for 3-D ICs n FIGURE 10-8 Block diagram of the 3-D test IC. Each block has an area of approximately 1 mm 2 . The remaining area is reserved for the I/O pads (the grey rectangles). 3 mm 40 39 1 2 3 4 5 6 7 8 26 31 30 38 37 36 35 34 33 32 Block A Block C 29 28 28 27 3 mm ~1 mm 14 15 9 10 11 12 13 25 Block B Block D 24 23 ~1 mm 16 17 18 19 20 21 22 the circuit and load conditions for the clock distribution networks under investigation. The logic is repeated in each plane and includes n n n n n Pseudorandom number generators A crossbar switch Control logic for the crossbar switch Groups of 4-bit counters Current loads and an output circuit for probing The pseudorandom number generators are based on the technique described in [317], which uses linear feedback shift registers and XOR operations to generate a random 16-bit word every clock cycle after the first few cycles required to initialize the generator. The physical lay- out of one random number generator is illustrated in Figure 10-10. A total of nine pseudorandom generators are used in each circuit block, connected by groups of three to the crossbar switch within each plane. A classic crossbar switch with six input and output ports is included in each plane, where the width of each port is 16 bits. Three of the six