Three-dimensional Integrated Circuit Design > Chapter 4: Interconnect Prediction Models

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Three-dimensional Integrated Circuit Design

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Table of Contents

Front Cover

Three-Dimensional Integrated Circuit Design

Chapter 1: Introduction

Chapter 2: Manufacturing of 3-D Packaged Systems

Chapter 3: 3-D Integrated Circuit Fabrication Technologies

Chapter 4: Interconnect Prediction Models

4.1. Interconnect Prediction Models for 2-D Circuits

4.2. Interconnect Prediction Models for 3-D ICs

4.3. Projections for 3-D ICs

4.4. Summary

Chapter 5: Physical Design Techniques for 3-D ICs

Chapter 6: Thermal Management Techniques

Chapter 7: Timing Optimization for Two-Terminal Interconnects

Chapter 8: Timing Optimization for Multiterminal Interconnects

Chapter 9: 3-D Circuit Architectures

Chapter 10: Case Study: Clock Distribution Networks for 3-D ICs

Chapter 11: Conclusions

Appendix A: Enumeration of Gate Pairs in a 3-D IC

Appendix B: Formal Proof of Optimum Single Via Placement

Appendix C: Proof of the Two-terminal Via Placement Heuristic

Appendix D: Proof of Condition for Via Placement of Multiterminal Nets

References

Index

Chapter Interconnect Prediction Models In deep submicrometer technologies, the interconnect resistance has increased significantly, profoundly affecting the signal propagation characteristics across an IC. On-chip interconnects have, therefore, become the primary focus in modern circuit design. Considering the broad gamut of interconnect issues, such as speed, power consump- 4

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Chapter 4: Interconnect Prediction Models - Pg. 65