Three-dimensional Integrated Circuit Design > Chapter 6: Thermal Management Techniques > 6.4. Summary

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Three-dimensional Integrated Circuit Design

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Table of Contents

Front Cover

Three-Dimensional Integrated Circuit Design

Chapter 1: Introduction

Chapter 2: Manufacturing of 3-D Packaged Systems

Chapter 3: 3-D Integrated Circuit Fabrication Technologies

Chapter 4: Interconnect Prediction Models

Chapter 5: Physical Design Techniques for 3-D ICs

Chapter 6: Thermal Management Techniques

6.1. Thermal Analysis of 3-D ICs

6.2. Thermal Management Techniques without Thermal Vias

6.3. Thermal Management Techniques Employing Thermal Vias

6.4. Summary

Chapter 7: Timing Optimization for Two-Terminal Interconnects

Chapter 8: Timing Optimization for Multiterminal Interconnects

Chapter 9: 3-D Circuit Architectures

Chapter 10: Case Study: Clock Distribution Networks for 3-D ICs

Chapter 11: Conclusions

Appendix A: Enumeration of Gate Pairs in a 3-D IC

Appendix B: Formal Proof of Optimum Single Via Placement

Appendix C: Proof of the Two-terminal Via Placement Heuristic

Appendix D: Proof of Condition for Via Placement of Multiterminal Nets

References

Index

6.4 Summary 131 3-D MST, routing congestion estimation Signal interplane via assignment YES Congestion or temperature violations? or temperature improvement? Evaluating temperature and sensitivity analysis for hot spots NO Post thermal via and wire insertion LP-based thermal via and wire insertion Rip-up and route END

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Chapter 6: Thermal Management Techniques > 6.4. Summary - Pg. 131