18 CHAPTER 1 Introduction RTL to Boolean Functions Technology-Independent Optimizations Technology Mapping Technology-Dependent Optimizations Test Logic Insertion FIGURE 1.8 Logic synthesis flow. This additional effort may seem to be avoidable with proper consideration given to undefined logic values in the function model. However, developing a func- tional model that initializes the same as a gate-level description requires consider- able effort and knowledge of the gate-level structure of a circuit. Hence, the