32 CHAPTER 1 Introduction Example 1.2 Figure 1.21a shows a chip floorplan of four modules and the power/ground network. As shown in the figure, we refer to a pad feeding supply voltage into the chip as a power pad, the power line enclosing the floorplan as a core ring, a power line branching from a core ring into modules inside as a power trunk, and a pin in a module that absorbs current (connects to a core ring or a power trunk) as a P/G pin. To ensure correct and reliable logic operation, we will minimize the voltage drops from the power pad to the P/G pins in a power/ground network. Figure 1.21a shows an instance of voltage drop in the power supply line, in which the voltage drops by almost 26% at the right- most P/G pin. Figure 1.21b shows that by having a different chip floorplan, the worst- case voltage drop is reduced to approximately 5% [Liu 2007]. Recent research showed that a 5% voltage drop in supply voltage might slow down circuit performance by as much as 15% or more [ Yim 1999]. Furthermore, it is typical to limit the voltage drop within 10% of the supply voltage to guarantee proper circuit operation. Therefore, volt- age drop is a first-order effect and can no longer be ignored during the design process. 1.5 CONCLUDING REMARKS The sophistication and complexity of current electronic systems, including printed circuit boards (PCBs) and integrated circuits (ICs), are a direct result of electronic design automation (EDA). Conversely, EDA is highly dependent on the power and performance of ICs, such as microprocessors and RAMs used to construct the computers on which the EDA software is exe- cuted. As a result, EDA is used to develop the next generation of ICs, which, in turn, are used to develop and execute the next generation of EDA, and so on in an ever-advancing progression of features and capabilities. 1.62V 1.67V core ring P/G pin 1.72V 1.33V 1.53V 1.8V, power pad power trunk (a) 1.77V 1.76V 1.71V 1.74V 1.8V, power pad (b) FIGURE 1.21 Two floorplans with associated power/ground network structures: (a) Worst-case voltage drop at the P/G pins approximately 26% of the supply voltage. (b) Worst-case voltage drop approximately only 5% [Liu 2007].