10.6 Exercises 625 [Yuh 2004b] are extensions of O-tree [Guo 1999], B*-tree [Chang 2000], and Transitive Closure Graph (TCG) [Lin 2001] for 2-D packing, respectively. Furthermore, heat dissipation is the most critical challenge of system-in-package design, sometimes called 2.5-D IC's (discrete layers are added into the traditional x and y spatial dimensions). Layer partitioning followed by 2-D floorplanning is often adopted to handle the thermal constraints for the 2.5-D IC designs [Cong 2004]. In addition to the floorplanning for VLSI modules, the floorplanning tech- niques can also be applied to other problems, such as system-on-chip test sched- uling [Wu 2005] and digital microfluidic biochip placement [Yuh 2006]. 10.5 CONCLUDING REMARKS Floorplanning is an essential design step for hierarchical, building-module design methodology. It provides valuable insights into the hardware decisions and estimation of various costs. The most popular floorplanning method resorts to the modeling of the floorplan structure and then optimizes the floorplan solutions with simulated annealing. There exist many floorplan representations