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CHAPTER 12 Global and detailed routing > 12.2 Problem definition - Pg. 689

12.2 Problem definition 689 12.2 PROBLEM DEFINITION The problem definition for the general routing problem is as follows: Inputs: 1. 2. 3. 4. A placed layout with fixed locations of chip blocks, pins, and pads A netlist A timing budget for each critical net A set of design rules for manufacturing process, such as resistance, capac- itance, and the wire/via width and spacing of each layer Output: Wire connection for each net presented by actual geometric layout objects that meet the design rules and optimize the given objective, if specified. 12.2.1 Routing model Routing in a modern chip is typically a very complex process, and it is thus usu- ally hard to obtain solutions directly. Most routing algorithms are based on a graph-search technique guided by the congestion and timing information asso-