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CHAPTER 14 Fault Simulation and Test Gen... > 14.4 Test Generation - Pg. 876

876 CHAPTER 14 Fault simulation and test generation multiple-pass fault simulation is to partition the faults into smaller groups, each of which is simulated independently. If the faults are well partitioned, multiple-pass fault simulation prevents the memory explosion problem. To further reduce the fault simulation time, distributed fault simulation approaches may be used. Distributed fault simulation divides the whole fault simulation into smaller tasks, each of which is performed independently on a separate processor. There are several alternatives to fault simulation. The fault-sampling technique was proposed to simulate only a sampled group of faults [Butler 1974]. Critical path tracing is another alternative to fault simulation [Abramovici 1984]. Instead of performing actual fault simulation, the statistical fault analysis (STAFAN) approach proposes to use probability theory to estimate the expected value of fault coverage [ Jain 1985]. These alternatives to fault simulation have also been extensively discussed in [Abramovici 1994], [Bushnell 2000], and [Wang 2006]. 14.4 TEST GENERATION First, consider the single stuck-at fault model. Figure 14.20 shows a circuit with a single stuck-at fault in which signal d is tied to logic 1 (d/1). A logic 0 must be applied to node d from the primary inputs of the circuit to produce a difference between the fault-free (or good) circuit and the circuit with the stuck-at fault pres- ent. Next, to observe the effect of the fault, a logic 1 must be applied to signal c. So, if the fault d/1 is present, it can be detected at the output e with the derived vec- tor. Test generation attempts to generate test vectors for every possible fault in the circuit. In this example, in addition to the d/1 fault, faults such as a/1, b/1, and e/1 are also targeted by the test generator. Because some of the faults in the circuit can be logically equivalent, no test can be obtained to distinguish between them. Thus, equivalence fault collapsing as described in Section 14.2 is often used to identify equivalent faults a priori to reduce the number of faults that must be targeted [Abramovici 1994; Bushnell 2000; Jha 2003]. Subsequently, the ATPG is only concerned with generating test vectors for each fault in the collapsed fault list. 14.4.1 Random test generation Random test generation (RTG) is one of the simplest methods for generating vectors. Vectors are randomly generated and fault-simulated (or fault-graded) on the circuit under test (CUT). Because no specific fault is targeted, the a b c stuck-at 1 d e FIGURE 14.20 Example of a single stuck-at fault.