References 913 a. Generate a test sequence for the target fault by use of only 5-valued logic. b. Generate a test sequence for the target fault by use of 9-valued logic. 14.16. (Sequential ATPG) Given a sequential circuit, is it possible that two stuck-at faults, a/0 and a/1, are both detected by the same vector v i in a test sequence v 0 , v 1 , . . . , v k ? 14.17. (Sequential ATPG) Consider an iterative logic array (ILA) expansion of a sequential circuit, where the initial pseudo primary inputs are fully controllable. Show that the states reachable in successive time frames of the ILA shrink monotonically. 14.18. (Bridging Faults) Consider a bridging fault between the outputs of an AND gate x ¼ ab and an OR gate y ¼ c þ d. What values to abcd would induce the largest current in the bridge? ACKNOWLEDGMENTS We thank Professor Hank Walker of the University of A&M for contributing a portion of the