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CHAPTER 2 Fundamentals of CMOS design > 2.7 Concluding remarks - Pg. 92

92 CHAPTER 2 Fundamentals of CMOS design One of the advantages of this dynamic memory partitioning technique that uses isolation nodes is the shared bit lines for the two ports. The length of active bit lines for both ports is shorter. Therefore, it reduces the silicon foot- print of multi-port cache memory and improves bit-line response time. Another advantage is the low-power dissipation, because the shared bit line consumes no more power than the single-port configuration. In addition, leak- age current remains the same as it is in a single-port configuration. This is because no dedicated bit lines and access transistors are used for the second port. By the use of local sense amplifiers and port multiplexing, this dynamic memory partitioning technique can be applied to on-chip cache memory with more than two ports. The same technique is applicable to DRAM. The disad- vantage is that a port may need to pass through several isolation nodes to access a memory cell. The channel resistance of the pass transistors imple- menting the isolation nodes adds to the bit line response time. However, as the technology advances down to the 32-nanometer node and below, transis- tor channel resistance will become insignificant compared with wire resis- tance of the bit lines. 2.7 CONCLUDING REMARKS CMOS technology has been the backbone of the many advances that have taken place in the past two decades, powering consumer appliances, automotives, personal and scientific computing, as well as many fascinating science and space explorations. Its advances have also made electronic design automation (EDA) tools possible and readily accessible to engineers. It is ironic that CMOS chips now power the computers on which engineers rely to design new chips. This chapter is intended to stimulate the reader's interest in the topic and pro- vide background information for the reader to relate CMOS design to the EDA techniques to be discussed in the subsequent chapters. New CMOS circuit technologies are still being developed. Currently, major improvements center on three fronts: transistors are used more efficiently to provide more computing and functionality, increasing circuit speed, and con- suming less power. This chapter has provided some examples in all three of these improvements. For readers who wish to explore further on CMOS design, refer to more recent textbooks cited in the chapter and IEEE publications such as IEEE Journal of Solid-State Circuits ( JSSC) and IEEE International Solid- State Circuit Conference (ISSCC). 2.8 EXERCISES The following transistor parameters are used in Exercises 2.1 to 2.13: