Electronic Design Automation > CHAPTER 5 Electronic system-level design and high-level synthesis

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Electronic Design Automation

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Table of Contents

Front Cover

Electronic Design Automation: Synthesis, Verification, and Test

CHAPTER 1 Introduction

CHAPTER 2 Fundamentals of CMOS design

CHAPTER 3 Design for testability

CHAPTER 4 Fundamentals of algorithms

CHAPTER 5 Electronic system-level design and high-level synthesis

5.1 Introduction

5.2 Fundamentals of High-level synthesis

5.3 High-level synthesis algorithm overview

5.4 Scheduling

5.5 Register binding

5.6 Functional unit binding

5.7 Concluding remarks

5.8 Exercises

Acknowledgments

References

CHAPTER 6 Logic synthesis in a nutshell

CHAPTER 7 Test synthesis

CHAPTER 8 Logic and circuit simulation

CHAPTER 9 Functional verification

CHAPTER 10 Floorplanning

CHAPTER 11 Placement

CHAPTER 12 Global and detailed routing

CHAPTER 13 Synthesis of clock and power/ground networks

CHAPTER 14 Fault Simulation and Test Generation

Index

CHAPTER Electronic system-level design and high-level synthesis Jianwen Zhu University of Toronto, Toronto, Canada Nikil Dutt University of California, Irvine, California 5 ABOUT THIS CHAPTER

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CHAPTER 5 Electronic system-level design and high-level synthesis - Pg. 235