Electronic Design Automation > CHAPTER 6 Logic synthesis in a nutshell > 6.1 Introduction

Table of Contents

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Table of Contents

Front Cover

Electronic Design Automation: Synthesis, Verification, and Test

CHAPTER 1 Introduction

CHAPTER 2 Fundamentals of CMOS design

CHAPTER 3 Design for testability

CHAPTER 4 Fundamentals of algorithms

CHAPTER 5 Electronic system-level design and high-level synthesis

CHAPTER 6 Logic synthesis in a nutshell

6.1 Introduction

6.2 Data Structures for Boolean representation and reasoning

6.3 Combinational logic minimization

6.4 Technology mapping

6.5 Timing analysis

6.6 Timing optimization

6.7 Concluding remarks

6.8 Exercises

Acknowledgments

References

CHAPTER 7 Test synthesis

CHAPTER 8 Logic and circuit simulation

CHAPTER 9 Functional verification

CHAPTER 10 Floorplanning

CHAPTER 11 Placement

CHAPTER 12 Global and detailed routing

CHAPTER 13 Synthesis of clock and power/ground networks

CHAPTER 14 Fault Simulation and Test Generation

Index

CHAPTER Logic synthesis in a nutshell Jie-Hong (Roland) Jiang National Taiwan University, Taipei, Taiwan Srinivas Devadas Massachusetts Institute of Technology, Cambridge Massachusetts 6 ABOUT THIS CHAPTER What is logic synthesis? As the name itself suggests, logic synthesis is the pro-

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Contents

CHAPTER 6 Logic synthesis in a nutshell > 6.1 Introduction - Pg. 299