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CHAPTER 6 Logic synthesis in a nutshell > Acknowledgments - Pg. 400

400 CHAPTER 6 Logic synthesis in a nutshell mappings with respect to the pattern graphs of Figure 6.26. What is the optimum solution that you can get among different decomposition approaches? 6.30. (DAG Mapping as SAT Solving) Formulate the DAG mapping feasi- bility problem as a satisfiability problem. For the subject graph of Fig- ure 6.50 and the pattern graphs of Figure 6.26, what is the CNF formula representing feasible DAG mappings? ACKNOWLEDGMENTS The authors are grateful to Professor Robert Brayton and Dr. Alan Mishchenko of the University of California at Berkeley, and Professor Jianwen Zhu of the University of Toronto for valuable feedback on the manuscript. REFERENCES R6.0 Books [Brayton 1984] R. K. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Mini- mization Algorithms for VLSI Synthesis, Kluwer, 1984. [Brown 2003] F. M. Brown, Boolean Reasoning: The Logic of Boolean Equations, Dover, 2003. [Devadas 1994] S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, McGraw-Hill, 1994. [Garey 1979] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman, 1979. [Hassoun 2002] S. Hassoun and T. Sasao, Logic Synthesis and Verification, Kluwer, 2002. [Kohavi 1978] Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1978. [McGeer 1991] P. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Kluwer, 1991. [Mo 2004] F. Mo and R. K. Brayton, Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design, Kluwer, 2004. [Minato 1996] S. Minato, Binary Decision Diagrams and Applications to VLSI CAD, Kluwer, 1996. [Papadimitriou 1993] C. Papadimitriou, Computational Complexity, Addison Wesley, 1993. [Sapatnekar 2004] S. Sapatnekar, Timing, Springer, 2004. [Scholl 2001] C. Scholl, Functional Decomposition with Applications to FPGA Synthesis, Kluwer, 2001. [Sutherland 1999] I. Sutherland, R. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Cir- cuits, Margan Kaufmann, 1999. [Villa 1997] T. Villa, T. Kam, R. K. Brayton, and A. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Logic Optimization, Kluwer, 1997. R6.1 Introduction [ABC 2005] Berkeley Logic Synthesis and Verification Group, ABC: A system for sequential synthesis and verification, http://www.eecs.berkeley.edu/$alanmi/abc/, 2005. [Brayton 1987] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, MIS: Multiple-level interactive logic optimization system, IEEE Trans. on Computer-Aided Design, 6(6), pp. 1062­1081, November 1987.