564 CHAPTER 9 Functional verification 9.8 EXERCISES 9.1. (Line Coverage) Suppose that the module in Box 9.11 was specified in your Verilog HDL design: BOX 9.11 1. module test; 2. reg X, Y, Z; 3. initial 4. begin 5. X ¼ 1 0 b0; 6. Y ¼ 1 0 b1; 7. if (X) 8. Z ¼ Y; 9. else 10. Z ¼ $Y; 11. end 12. endmodule Calculate the line coverage after simulation and identify the line or lines that has/have not been covered. 9.2. (Toggle Coverage) Suppose that the following module in Box 9.12 was specified in your Verilog HDL design: BOX 9.12 1. module test; 2. reg [2:0] X; 3. initial 4. begin 5. X ¼ 3 0 b000; 6. #100; 7. X ¼ 3 0 b110; 8. #100; 9. X ¼ 3 0 b010; 10. #100; 11. end 12. endmodule After simulation, the register would have achieved a total toggle per- centage of 50%. Please identify which toggles are missing.