42 CHAPTER 4 Interconnects and switching fabrics Input 1 Output 1 Input 1 Output 1 Input N ... Output N ... Input N ... Output N ... (a) Output queue 1 (b) Input 1 ... Output queue N Output 1 Input 1 Output 1 Input N ... ... ... ... ... Output N Input N Output N (c) FIGURE 4-5 Input and output queuing switches. 1000 Input Queuing Output Queuing Average Packet Delay (d) 100 10 1 0.2 0.3 0.4 Load 0.5 0.6 0.7 0.8 0.9 1 FIGURE 4-6 Average packet delay for input and output queuing switches. be targeted to a specific output with a uniform probability distribution among all outputs. As Figure 4-6 indicates clearly, input queuing switches cannot achieve output throughput more than (almost) 60%, even under heavy load conditions. This occurs because input queuing switches suffer from a blocking phenomenon, called Head-of-Line (HoL) blocking, which limits switch performance. HoL blocking is