Index Note: Page numbers followed by f indicate figures and t indicate tables. A Accelerator, see Packet ACK flag, 298 Adapters, network effective throughput, 68, 69f intelligent DMA unit, 75­77, 75t, 76f, 77t memory organization management schemes detached configuration, 86, 86f distributed configuration, 87, 87f overview, 84­87, 85f memory management unit and processor with local memory, 73­75, 73f, 74f, 75t memory management unit with local memory, 70­73, 71f, 72f multiprocessor processing element, see Cell Broadband Engine operation analysis, 66­70, 66f, 69f overview, 63­64, 64f packet reception, 66f structure, 22f, 23, 64­66, 64f Address Resolution Protocol (ARP), 292 payload inspection scenarios, 172­173 search patterns, 173­174 regular expression matching algorithms, 178 Application-specific integrated circuit (ASIC), 212­213 Area-based quad tree, rule matching in network layer, 154­155, 154f ARM processor, adapter effective throughput, 68, 69f, 72f, 74f, 76f ARP, see Address Resolution Protocol ARTEMIS, 4, 5f ASIC, see Application-specific integrated circuit Asymmetric key cryptography, 202­203, 204f Asynchronous Transfer Mode (ATM), packet switching, 26 ATM, see Asynchronous Transfer Mode Authenticity, security, 200 Availability, security, 200