70 CHAPTER 5 Network adapters elsewhere [118]; simulation results are the same as in Meleis and Serpanos [118]. For ARM processor configuration, we consider use of the 64-bit AMBA High- performance Bus (AHB), operating at 133 MHz [7]. Importantly, ARM11 has a processing power of 660 MIPS [6] and a task-switching delay equal to 30 inst- ructions [98], achieving low interrupt latency for interrupt-driven applications. In regard to protocol processing at the PE, we assume that the PE executes the LLC protocol with a critical path of 351 instructions as used elsewhere [118], based on data provided in [174]. Figure 5-4 shows effective throughput of the adapter as a function of packet arrival rate. Throughput is expressed in bytes per second, while the packet arrival rate is expressed in packets per second. Every plot shows three curves, one for a different scenario where fixed-size-length packets--different length for each scenario--arrive at the adapter link. The three packet lengths considered are 64, 256, and 1024 bytes. As the plots illustrate, the adapter throughput increases as packet arrival rate increases until it reaches a threshold value, after which per- formance remains steady. This is the maximum throughput achievable with the present adapter configuration. MEMORY ORGANIZATION Analysis of the reception process enables an architect to identify several limitations that can be addressed. In the basic adapter, shown in Figure 5-2, the processor executes all memory management operations in addition to protocol code execution. Furthermore, the processor remains idle during packet data movement on the bus because it cannot access memory and thus it can neither access data nor code, which is also stored in the same memory used by the DMA. Architectural enhancements are necessary to enable higher utilization of the processor, as well as off-loading of memory management operations, so that the processor can be dedicated to protocol execution. Taking into account architectural concepts from general-purpose pro- cessors, one can employ a specialized memory management unit (MMU) for the management of memory as well as a partitioned memory structure in order to enable parallelism among data transfer, memory management, and protocol execution. The following discussions describe and evaluate these architectural enhancements. Memory management unit with local memory Operation of the basic adapter requires that the processor performs at least four memory management operations during packet reception and two more during processing the packet header. These operations can be assigned to a specialized hardware unit, the Memory Management Unit, which implements all memory management operations. In principle, these operations can be executed in parallel with data movement and/or protocol processing. For example, a new free buffer address can be identified or buffer enqueueing (or dequeueing) can be performed in parallel with data movement to memory. However, such concurrency is achievable