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References - Pg. 301

References [1] Advanced Research & Technology for EMbedded Intelligence and Systems, ARTEMIS. http://www.artemis.eu/. [2] M.J. Akhbarizadeh, M. Nourani, D.S. Vijayasarathi, P.T. Balsara, PCAM: A ternary CAM optimized for longest prefix matching tasks, in: Proceedings of the IEEE Interna- tional Conference on Computer Design (ICCD), San Jose, CA, October 2004, pp. 6­11. [3] T.E. Anderson, S.S. Owicki, J.B. Saxe, C.P. Thacker, High-speed switch scheduling for local-area networks, ACM Transactions on Computer Systems 1 (4) (1993). [4] A. Andriahantenaina, A. Greiner, Micro-network for SoC: Implementation of a 32-port SPIN network, in: Proc. of Design, Automation and Test in Europe Conference and Exposition (DATE), Munich, Germany, March 2003, pp. 11128­11129. [5] G. Apostolopoulos, D. Aubespin, V. Peris, P. Pradhan, D. Saha, Design, implementa- tion and performance of a content-based switch, in: Proc. of IEEE INFOCOM 2000, Tel Aviv, Israel, March 2000, pp. 1117­1126. [6] ARM Ltd., ARM Processor Bus Reference. http://www.arm.com/. [7] ARM Ltd., ARM1136 Processor. http://www.arm.com/. [8] ARTEMIS Strategic Research Agenda Working Group, ARTEMIS Strategic Research Agenda, first ed., March 2006. https://www.artemisia-association.org/downloads/ SRA_MARS_2006.pdf. [9] The ATM Forum, ATM User-Network Interface Specification Version 3.0, July 1993. [10] F. Baker, Requirements for IP version 4 routers. RFC 1812, Network Working Group, June 1995.