244 CHAPTER 13 Networks on chips capacitive load C L , and (iv) each output drives a register (B 4 ) that stores the incom- ing data, the total bus delay is the sum of three components: d b ¼ d in þ d w þ d out ; where d in is the delay to drive buffer B 1 and the cascaded buffers B 2 , d w is the latency on the bus wire, and d out is the delay of B 3 driving register B 4 . Considering that the sequence of buffers B 1 , B 2 , and B 3 needs to be sized so that the buffers constitute a cascade driving a load of N buffers B 3 , that is, N Á C L , and disregarding the delay of the long wire, the delay (d in þ d out ) À d B4 , where d B4 is the delay of the last buffer B 4 , is computed using the formula for exponen- tially tapered buffers [187]: C L 1=N t min ðd in þ d out Þ À d B4 ¼ k N C g In this equation, k is the number of stages in the cascaded buffers and t min is the delay to drive a minimum size load with capacitance C g , that is, C g and t min are constants that depend on the technology. The wire delay d w is a function of the length L b (L b ¼ N) and is calculated as