5.2 Virtual Links Using send , receive , and a Bounded Buffer 215 pace. The processors may have different speeds and take interrupts at different times, or instructions may hit in the cache on one processor and miss on another, so there is no way to predict the relative timing of the load and store instructions that the threads issue. This scenario is an instance of asynchronous interpreters (described in Section 2.1.2). Thus, we should make no assumptions about the sequence in which the mem- ory operations of the two threads execute. When analyzing the concurrent execution of two threads, both executing instructions 6 through 8 in Figure 5.5, we can assume they execute in some serial sequence (because the bus arbiter will order any memory operations that arrive at the bus at the same time). However, because the relative speeds of the threads are unpredictable, we can make no assumptions about the order in the sequence. We represent the execution of instruction 6 by thread A as "A6". Using this repre- sentation, we see that one possible sequence might be as follows: A6, A7, A8, B6, B7, B8. In this case, the program works as expected. Suppose we just started, so variables in and out are both zero. Thread A performs all of its three instructions before thread B performs any of its three instructions. With this order, thread A inserts an item in entry 0 and increments in from 0 to 1. Thread B adds an item in entry 1 and increments in