164 Chapter 4 In short, an I/O device can be connected directly to the master processor via I/O ports (proc- essor pins) if the I/O devices are located on the board, or it can be connected indirectly using a communication interface integrated into the master processor or a separate IC on the board and the communication port. The communication interface itself is what is either connected directly to the I/O device or the device's I/O controller. For off-board I/O devices, the relative board I/O components are interconnected via I/O buses. 4.3.2 Interfacing an I/O Controller and the Master CPU In a subsystem that contains an I/O controller to manage the I/O device, the design of the interface between the I/O controller and master CPU--via a communications interface--is based on four requirements: · An ability of the master CPU to initialize and monitor the I/O controller. I/O control- lers can typically be configured via control registers and monitored via status registers. These registers are all located on the I/O controller. Control registers are data registers that the master processor can modify to configure the I/O controller. Status registers are read-only registers in which the master processor can get information as to the state of the I/O controller. The master CPU uses these status and control registers to communicate and/or control attached I/O devices via the I/O controller. A way for the master processor to request I/O. The most common mechanisms used by the master processor to request I/O via the I/O controller are special I/O instruc- tions (I/O mapped) in the ISA and memory-mapped I/O, in which the I/O controller registers have reserved spaces in main memory. A way for the I/O device to contact the master CPU. I/O controllers that have the abil- ity to contact the master processor via an interrupt are referred to as interrupt driven I/O. Generally, an I/O device initiates an asynchronous interrupt requesting signaling to indicate (for example) control and status registers can be read from or written to. The master CPU then uses its interrupt scheme to determine when an interrupt will be discovered. Some mechanism for both to exchange data. This refers to how data is actually exchanged between the I/O controller and the master processor. In a programmed transfer, the master processor receives data from the I/O controller into its registers, and the CPU then transmits this data to memory. For memory-mapped I/O schemes, DMA (direct memory access) circuitry can be used to bypass the master CPU entirely. DMA has the ability to manage data transmissions or receptions directly to and from main memory and an I/O device. On some systems, DMA is integrated into the mas- ter processor, and on others there is a separate DMA controller. Essentially, DMA requests control of the bus from the master processor. · · · www.n e wn e s p res s .c o m