202 Logic/HDL synthesis technology , 166 LUT-based logic block , 20­1 LUT vs. distributed RAM vs. SR , 22­3 LUT/CLB-level netlist , 147 Index M MAC , see Multiply-and-accumulate Main FPGA fabric , 30­1 Main memory (MEM) , 140 Mapping , 84 Mathworks, The , 126 , 127 , 133 MATLAB , 127 , 132 Medium-grained architecture , 19 Microarchitecture definition tasks , 108 Microblaze , 144 Microcontroller , 108 Microprocessor unit (MPU) , 140 Microsecond logic , 29 , 145 Millisecond logic , 29­30 , 145 Min:typ:max delays , 160 , 161 Mixed-language designs , 99­100 and verification environments , 124­5 Mixed-language simulation , 159­60 Mixed-level design capture environment , 95 Parallel multiplexers vs. serial multiplexers , 103­4 Parallel statement, in augmented C/C language , 118 Partitioning design, into hardware and software components , 145­7 Performance analysis , 183 Phase-locked loops (PLLs) , 36 and clock conditioning circuitry , 66 Physical layer communications , 4 Physically aware synthesis technology , 167 PicoBlaze , 144 Picosecond and nanosecond logic , 29 , 145 Pilkington Microelectronics (PMEL) , 192 Pipelined design , 163 , 164 Pipelining , 61 , 62­3 Place-and-route software , 82 , 85 PLDs , see Programmable logic devices Polygonal editors , 81 Post-place-and-route simulation , 86 Pragma , 107 , 177 , 179 Procedural , 177 Programmable logic devices (PLDs) , 1­2 Programming (configuring), an FPGA , 49