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Chapter 9: Implementation of FFT on Gene... > THE REFERENCE PLATFORMS - Pg. 167

Implementation of FFT on General-Purpose Architectures for FPGA THE REFERENCE PLATFORMS In order to compare the performance of the two architectures described above, we introduce two single-core reference platforms, one for the integer case, one for the floating-point. The reference platforms are of the architectural form depicted in Figure 5. For the integer case the processor core used is COFFEE whereas for the floating-point case it is CAPPUCCINO. Since both of the processors can be pro- grammed in C, it is possible to run any C applica- tion on the reference platforms. It is also possible to quantify the speed-up obtained using the re- configurable platform or the MP-SoC platform. The use of the same reference platform allows a fair comparison between the two platforms under study. Table 6 summarizes the maximum operating frequencies in the reference platforms according The FFT Algorithm The FFT algorithm that we mapped onto the two platforms is based on radix-2 decimation in frequency, introduced by Cooley and Tukey (1965). The algorithm was chosen because of its scalability and intrinsic support of parallelization. The idea behind the radix-2 decimation is that an N-point FFT can be implemented using a dedicated stage plus two N/2-point FFTs. The dedicated stage is composed of N/2 butterfly op- erations. Iterating this procedure, we can end up with a 2-point FFT that corresponds to a simple butterfly operation between 2 complex values. This means that an N-point FFT can be decomposed in a succession of n stages, where n is equal to the base 2 logarithm of N and each stage processes N complex values using N/2 butterflies. The main issue for the mapping of a radix-2 algorithm on our platforms is to decide how each