209 A Design Methodology of MIN- Based Network for MPPSoC on Reconfigurable Architecture Y. Aydi University of Sfax, Tunisia M. Baklouti University of Sfax, Tunisia & University of Lille, France Ph. Marquet University of Lille, France M. Abid University of Sfax, Tunisia J.L. Dekeyser University of Lille, France Chapter 9 ABSTRACT Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates archi- tectural parameters which have a huge impact on design costs. After validating the functional model, DOI: 10.4018/978-1-60960-086-0.ch009 Copyright © 2011, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.