Introduction to Synchronous State Machine Design and Analysis 253 Failure to meet the setup and hold-time requirements of the memory flip-flops in an FSM can cause improper sampling of the data that could, in turn, produce erroneous transitions, or even metastability. A change of the data input at the time CK is in its sampling interval can produce a runt pulse, a pulse that barely reaches the switching threshold. An incompletely sampled runt pulse may cause erroneous FSM behavior. As an example of proper and improper sampling of an input, consider a portion of the resolver state diagram for an RET D flip-flop shown in Figure 5.54a. Assuming that the FSM is in state a and that the rising edge of CK is to sample the D input waveform, two sampling possibilities are illustrated by the voltage waveforms for CK and D in Figure 5.54b. Proper sampling occurs when the data input D is stable at logic level 1 in advance of the rising edge of CK and maintained during the sampling interval. Improper sampling results when D changes during the sampling interval. Sampling Interval CK a 00 CK DCK DCK