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Chapter 5: Introduction to Synchronous S... > 5.9 Latches and Flip-Flops with Seri... - Pg. 248

248 Chapter 5 Q M (H) Q M (H) D(H) CK D M Q Q D S Q Q Q(H) Q(L) D(H) CK D M Q Q D S CK Q Q Q(H) Q(L) (a) (b) Figure 5.48: The D data lockout flip-flop (a) All edge triggered flip-flop variety (b) Same as (a) except with an FET D latch as the slave stage 5.9 Latches and Flip-Flops with Serious Timing Problems: A Warning With very few exceptions, two-state flip-flops have serious timing problems that preclude their use as memory elements in synchronous state machines. Presented in Figure 5.49 are four examples of two-state latches that have timing problems--none have the data lockout feature. The RET D latch (a) becomes transparent to the input data when CK ¼ 1, causing flip-flop action to cease. The three remaining exhibit even more severe problems. For example, the FET T latch (b) will oscillate when T Á CK ¼ 1, and the RET JK latch (c) will oscillate when JK Á CK ¼ 1, requiring that J ¼ K ¼ CK ¼ 1, as indicated in the figure. Notice that the branching conditions required to cause any of D+CK T+CK J+CK ST+CK 0 DCK 1 DCK Q t TCK 0 TCK 1 Q t JCK 0 KCK 1 Q t (S+T)CK 0 SCK 1 Q t D+CK Transparency for CK = 1 (a) T+CK Oscillation if CK = 1 (b) K+CK Oscillation if J = K = CK = 1 (c) (d) S+CK Oscillation if ST.CK = 1 Figure 5.49: Timing problems in latches (a) RET D latch (b) FET T latch (c) RET JK latch (d) FET ST latch