Getting Started 17 n Example 1­22. Entity Code Entity test_code Is Port( clk : In std_logic; start_ counter : In std_logic; ready_signal : Inout std_logic; sound_alarm : Out std_logic); End test_code; -- input clock -- starts counter when door is opened -- indicates alarm status -- alarms buzzer when timer expires n 1.7.4. Architecture Section The architecture section is where you write the design code, see Example 1­23. The design code describes the functions by using the software-like programming language VHDL. Now, you use the defined functions, data types, and so for the package(s) declared or called out in the library declaration section. Your design receives and passes design data using the input, bidirectional (inout), and output ports defined in the entity section.