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6.5. Synthesis Output Files > 6.5.1. Netlists - Pg. 138

138 Chapter 6 Synthesis Outputs EDIF Xilinx Place and Route Altera's Place and Route Netlists EDIF Functional Netlist Simulator Status Report Resource Utilization Preoptimized RTL Schematic Views Postsynthesized Technology Figure 6­8: Synthesis Outputs