194 Chapter 8 Host JTAG Cable Test Pins TDI TDO TCK TMS TDI TDO TCK TMS PROM Configuration Lines FPGA Figure 8­4: JTAG Setup. Note: Multiple pins are represented by thick pin lines. connector on a board that connects to the JTAG-compatible nonvolatile memory device, see Figure 8­4. The JTAG device configures the slave mode FPGA on power-up. JTAG also supports daisy-chain configurations. Generally, a GUI is provided to guide you through the program process. FPGA manufacturers generally offer JTAG programming tools, cables, and any necessary supplies. Often, they also provide a list of third party vendors or distributors where you can purchase JTAG materials. JTAG can be a great way to quickly incorporate design changes. I found this way to work well with demo boards, prototypes, and breadboards.