210 Appendix Component LogicGates Port ( number_1 : In std_logic_vector (3 Downto 0); ­­ setting initial value number_2 : In std_logic_vector (3 Downto 0) ­­ setting initial value or_out : Out std_logic_vector (3 Downto 0); nor_out : Out std_logic_vector (3 Downto 0); and_out : Out std_logic_vector (3 Downto 0); nand_out : Out std_logic_vector (3 Downto 0)); End Component LogicGates; Begin LogicGates1: LogicGates Port Map ( number_1 ¼> number_1, number_2 ¼> number_2, or_out ¼> or_out, nor_out ¼> nor_out,