APPENDIX Testbenches A­1. Adder and Subtractor Testbench Use this testbench to verify the adder and subtractor design in Chapter 2. An example of the simulated output is shown in Figure A­1. Run the simulation for 200.00 nsec. Library IEEE; Use IEEE.std_logic_1164.All; Use IEEE.std_logic_unsigned.All; Entity testbench Is End testbench; Architecture tb_MathematicalOperators Of testbench Is