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Chapter 3: FPGA Development Phases > 3.3. I/O Interfaces - Pg. 44

44 Chapter 3 situation would be if the device has insufficient resources to support the design changes, then a new device is required. If the new device is not a direct drop-in replacement--meaning pin-for- pin compatible (i.e., power and grounds are in the same location)--then the printed wiring board must be modified. More times than not, your design changes do not affect the hardware, especially if you have derated or left room in your device for growth. The amount of room for growth varies, but we talk more about this later in the book. The point I am trying to make is that FPGAs provide a lot of flexibility and opportunity to make design changes quickly. Xilinx, Altera, and Quicklogic are just a few companies that manufacture FPGAs. Even though there are several FPGA manufacturers, they all share the same basic architecture concept. It consists of three basic capabilities: input/output (I/O) interfaces, basic building blocks, and interconnections. Figure 3­1 shows a generic FPGA architecture. It shows some basic building blocks connected to other basic building blocks, which are also connected to I/O interfaces, where data are passed to external sources. This figure is not meant to represent any particular device or design; it is provided only as a way of showing how the three basic capabilities interrelate. In the following sections, you are provided additional information on each of the capabilities. 3.3. I/O Interfaces I/O interfaces are the mediums in which data are sent from internal logic to external sources and from which data are received from external sources. The interface signals can be unidirectional or bidirectional, single-ended or differential and could follow one of the different I/O standards. Some I/O standards are · · GTL (gunning transceiver logic). HSTL (high-speed transceiver logic). I/O Interfaces I/O I/O I/O I/O I/O I/O I/O I/O I/O Combinatorial Logic Combinatorial Logic I/O Basic Building Blocks I/O I/O Interconnections I/O Combinatorial Logic I/O Combinatorial Logic I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Figure 3­1: Generic FPGA Architecture