62 Chapter 4 n Example 4­1. Documenting a Requirement Change The original timing diagram shows a 50 MHz clock frequency with a conflicting 2 nsec time period. After verifying that 50 MHz is correct, 2 nsec is changed to 20 nsec, as shown in Figure 4­5, until the design package can be updated. Original provided by lead designer 50 MHz Clock 2 nsec On 1-28-09 lead designer confirmed 50 MHz is correct, changed from 2 nsec to 20 nsec 50 MHz Clock 20 nsec Figure 4­5: Corrected Timing Diagram n