Simulation 87 Edit design to correct timing & other errors, change logic & ... Edit design to correct synthesis & other errors, change logic & ... Edit design to correct logic errors, change design & ... Simulation RTL Design Resynthesize Recompile after design edit Functional RTL Output Functional Gate Level Synthesis Reimplement Recompile after design edit Gate Level Implementation Recompile after design edit Figure 5­3: Simulation Levels