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Chapter 6: Synthesis > 6.4. Synthesis Input - Pg. 136

136 Chapter 6 Design File HDL Synthesis Setup Input Design Constraints File Timing FPGA Manufacturer's Name Device Family AB2C50A VQ122BHX0825 J9876 5M Constraints Functional Netlist Device Information Design Netlist Device Type Package Speed Temperature Pin 1 Figure 6­6: Basic Synthesis Setup Information 6.4. Synthesis Input The input to the synthesis development phase is the design, VHDL code in our case. In addition to the design file are the user-defined constraints or limitations. The constraints may contain such things as timing or Vendor attributes. Acceptable design formats vary between synthesis tools, so make sure prior to creating your design or selecting your tool that the formats are compatible. Altera's Quartus II accepts · · · · · · · AHDL (Altera Hardware Description Language). VHDL. Verilog. System Verilog. Schematic capture. EDIF input files; Quartus II supports both .edif and .edn file extensions. Verilog Quartus mapping files; this is a node-level netlist in ASCII text format, generally created by an EDA synthesis tool, like Synopsys Synplify.