82 Chapter 5 But consider very carefully whether you want to face the additional complexity and headaches that result from enabling the use of nested interrupt calls. After all, if the interrupt service routines are short and efficient, the extra latency introduced by waiting for the current interrupt to be completed before a new one is serviced is going to be extremely small. If you determine that you don't really need it, make sure the NSTDIS control bit is set to prevent nesting: _NSTDIS = 1; // disable interrupt nesting (default) Post-Flight Briefing In this lesson we have seen how an interrupt service routine can be simple to code thanks to the language extensions built into the MPLAB C compiler, and the powerful interrupt control mechanisms offered by the PIC24 architecture. Interrupts can be an extremely efficient tool in the hands of the embedded-control programmer to manage multiple tasks while maintaining precious timing and resources constraints. At the same time, they can be a great source of trouble. In the PIC24 reference manual and the MPLAB C Compiler User Guide you will find more useful information than we could possibly cram into one single lesson. Finally, in this lesson we took the opportunity to learn more about the uses of Timer1 and the secondary oscillator, and we got a glimpse of the features of the new Real-Time Clock and Calendar (RTCC) module. Notes for the C Experts The interrupt vector table (IVT) is an essential part of the crt0 code segment for the PIC24. Actually, two copies of it are required to be present in the first 256 locations of the program memory. One is used during normal program execution, and the second (or Alternate IVT) during debugging. These tables account for most of the size of the crt0 code in all the examples we have been developing in these first five lessons. Subtract 256 words (or 768 bytes) from the file size of each example to obtain the "net" code size. Notes for the Assembly Experts The _ISRFAST macro can be used to declare a function as an interrupt service routine and to further specify that it will use an additional and convenient feature of the PIC24 architecture: a set of four shadow registers. By allowing the processor to automatically save the content of the first four working registers (W0­W3, i.e. the most frequently used ones) and most of the content of the SR register in special reserved locations, without requiring the use of the stack, the shadow registers provide the fastest possible interrupt response time. Naturally, since there is only one set of such registers, their use is limited to applications where only one interrupt will be serviced at any given time. This does not limit us to use only one interrupt in the entire application, but rather to use _ISRFAST only in applications that have all interrupts with the same priority level or, if multiple levels are in use, reserve the _ISRFAST options only for the interrupt service routines with the highest level of priority.