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    Front Cover
    Half Title Page
    The Definitive Guide to the ARM Cortex-M3
    Copyright Page
    Table of Contents
    Foreword
    Foreword
    Preface
    Acknowledgments
    Conventions
    Terms and Abbreviations
    Chapter 1. Introduction
    Chapter 2. Overview of the Cortex-M3
    Chapter 3. Cortex-M3 Basics
    Chapter 4. Instruction Sets
    4.1 Assembly Basics
    4.2 Instruction List
    4.3 Instruction Descriptions
    4.4 Several Useful Instructions in the Cortex-M3
    4.4.1 MSR and MRS
    4.4.2 More on the IF-THEN Instruction Block
    4.4.3 SDIV and UDIV
    4.4.4 REV, REVH, and REVSH
    4.4.5 Reverse Bit
    4.4.6 SXTB, SXTH, UXTB, and UXTH
    4.4.7 Bit Field Clear and Bit Field Insert
    4.4.8 UBFX and SBFX
    4.4.9 LDRD and STRD
    4.4.10 Table Branch Byte and Table Branch Halfword
    Chapter 5. Memory Systems
    Chapter 6. Cortex-M3 Implementation Overview
    Chapter 7. Exceptions
    Chapter 8. The Nested Vectored Interrupt Controller and Interrupt Control
    Chapter 9. Interrupt Behavior
    Chapter 10. Cortex-M3 Programming
    Chapter 11. Exception Programming
    Chapter 12. Advanced Programming Features and System Behavior
    Chapter 13. The Memory Protection Unit
    Chapter 14. Other Cortex-M3 Features
    Chapter 15. Debug Architecture
    Chapter 16. Debugging Components
    Chapter 17. Getting Started with the Cortex-M3 Processor
    Chapter 18. Porting Applications from the ARM7 to the Cortex-M3
    Chapter 19. Starting Cortex-M3 Development Using the GNU Tool Chain
    Chapter 20. Getting Started with the Keil RealView Microcontroller Development Kit
    Chapter 21. Programming the Cortex-M3 Microcontrollers in NI LabVIEW
    Appendix A. The Cortex-M3 Instruction Set, Reference Material
    Appendix B. The 16-Bit Thumb Instructions and Architecture Versions
    Appendix C. Cortex-M3 Exceptions Quick Reference
    Appendix D. Nested Vectored Interrupt Controller and System Control Block Registers Quick Reference
    Appendix E. Cortex-M3 Troubleshooting Guide
    Appendix F. Example Linker Script for CodeSourcery G++
    Appendix G. CMSIS Core Access Functions Reference
    Appendix H. Connectors for Debug and Tracers
    References
    Index
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    4.4 Several Useful Instructions in the Cortex-M3 > 4.4.5 Reverse Bit - Pg. 73

    4.4 Several Useful Instructions in the Cortex-M3 73 YoucansetuptheDIVBYZERObitintheNVICConfigurationControlRegistersothatwhena dividebyzerooccurs,afaultexception(usagefault)takesplace.Otherwise,<Rd>willbecome0ifa dividebyzerotakesplace. 4.4.4 REV, REVH, and REVSH REVreversesthebyteorderinadataword,andREVHreversesthebyteorderinsideahalfword.For example,ifR0is0x12345678,inexecutingthefollowing: REV R1, R0 REVH R2, R0 R1willbecome0x78563412,andR2willbe0x34127856.REVandREVHareparticularlyusefulfor convertingdatabetweenbigendianandlittleendian. REVSH is similar to REVH except that it only processes the lower half word, and then it sign extendstheresult.Forexample,ifR0is0x33448899,running: REVSH R1, R0 R1willbecome0xFFFF9988.