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Chapter 13. Transceiver Design Example > References
References
[1] L. L. Kan et al., “A 1-V 86-mW-RX 53-mW-TX Single-Chip CMOS Transceiver for WLAN IEEE 802.11a,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 1986–1998, Sept. 2007.
[2] K. Cai and P. Zhang, “The Effects of IP2 Impairment on an 802.11a OFDM Direct Conversion Radio System,” Microwave Journal, vol. 47, pp. 22–35, Feb. 2004.
[3] I. Vassiliou et al., “A Single-Chip Digitally Calibrated 5.15-5.825-GHz 0.18-?m CMOS Transceiver for 802.11a Wireless LAN,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2221–2231, Dec. 2003.
[4] C. Rapp, “Effects of HPA-Nonlinearity on a 4-DPSK/OFDM-Signal for a Digital Sound Broadband System,” Rec. Conf. ECSC, pp. 179–184, Oct. 1991.
[5] M. Simon et al., “An 802.11a/b/g RF Transceiver in an SoC,” ISSCC Dig. Tech. Papers, pp. 562–563, (also Slide Supplement), Feb. 2007.
[6] T.-C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 888–894, June 2003.
[7] A. Afsahi and L. E. Larson, “An Integrated 33.5 dBm Linear 2.4 GHz Power Amplifier in 65 nm CMOS for WLAN Applications,” Proc. CICC, pp. 611–614, Sept. 2010.
[8] A. Pham and C. G. Sodini, “A 5.8-GHz 47% Efficiency Linear Outphase Power Amplifier with Fully Integrated Power Combiner,” IEEE RFIC Symp. Dig. Tech. Papers, pp. 160–163, June 2006.
[9] B. Chang, J. Park, and W. Kim, “A 1.2-GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE J. Solid-State Circuits, vol. 31, pp. 749–754, May 1996.
