1. Verilog–VHDL comparison:

• Verilog and VHDL are the two most common logical view-construction and simulation environments in use. The student or interested engineer might find it useful to attempt to build a series of stdcell models (using only those constructs commonly used within stdcell models as opposed to those that can be used in a wider and more-extensive RTL netlist). These models should be developed with all state-dependent arcs possible in the two languages in order to see, in their own view, which is easier to learn and use and which is more bulletproof.

2. Unknown handling in various simulators:

• Many simulators are made to work with either or both of the previous two mentioned logical languages, including those that are compiled and those that are interpretive. It behooves the student or interested engineer to attempt to simulate the logical models of a stdcell library (either those that they built in the above exercise or those that they acquire from an extant library) in multiple different simulator environments in order to see how those various environments handle certain constructs within the logical models. Where there are differences, the student or interested engineer might be inclined to determine the offending constructs within the logical models and adjust them so that the models simulate correctly across all given simul....